1. Field of the Invention
The present invention relates to a method for testing a semiconductor device provided with a transistor circuit marking capable of causing damage which can be visually identified by latch-up to identify a chip on a wafer which has been determined as defective by a functional test, and a semiconductor device with a transistor circuit for marking.
2. Description of the Related Art
When a functional test on a wafer is conducted, it is necessary that chip determined as a defective is marked. Normally, marking of the defective chip is effected by using mechanical means such as an inker provided at a probing unit. There is the fear that a chip next to a defective chip may be erroneously marked when a marking position is shifted in a case of employing such mechanical means. There has been, thus, proposed a marking method by providing a special circuit in an LSI without using mechanical means.
FIG. 1 is a typical plan view of a semiconductor chip to describe a method for marking a semiconductor device as described in Japanese Patent Application Laid-Open No. 61-64137. This semiconductor chip 34 is provided with a marking dedicated pad 31, a GND pad 32 and a circuit for marking 33. The circuit for marking 33 consists of a material which can be easily fused such as aluminum. One end of the circuit 33 is connected to the marking dedicated pad 31 and the other end thereof is connected to the GND pad 32.
In the conventional semiconductor device, when the chip is determined as a defective by the wafer functional test, the circuit for marking 33 is fused by applying a high voltage or high current to the marking dedicated pad 31. Thereafter, the fused portion is visually identified and the defective chip is thereby screened.
Meanwhile, Japanese Patent Application Laid-Open No. 63-102332 discloses a method for identifying a defective chip wherein a thermal coloring matter or resin containing the thermal coloring matter is applied on the surfaces of chips of a semiconductor device in advance and a defective chip, if any, is colored by applying a current to the coloring matter and identified as such.
In addition, Japanese Patent Application Laid-Open No. 2-90549 discloses a semiconductor device having a memory cell for inputting and storing a case of a non-defective chip or defective.
Moreover, Japanese Patent Application Laid-Open No. 6-53292 discloses a method for inspecting a semiconductor device capable of detecting, for example, visually that a semiconductor integrated circuit part is abnormal by applying an excessive voltage to a power supply terminal of an operational check circuit part to thereby break the operational check circuit part.
Furthermore, Japanese Patent Application Laid-Open No. 9-199672 discloses a method for inspecting a semiconductor integrated circuit device having a structure in which a fuse is provided in the middle of each of the wirings connected to the first and second electrodes and to an internal circuit, a voltage exceeding input allowable level is supplied to both the first and second electrodes to disconnect the fuse, thereby stopping supplying power to the internal circuit of a defective chip.
The conventional technique described in Japanese Patent Application Laid-open No. 61-64137 has the following problems. First, if insufficient voltage or current is applied, the marking circuit 33 may not be fused. If so, a defective chip is determined as a non-defective. Second, contrary to the first, if an excessive current or voltage is applied, there is a fear of breaking not only a defective but also a chip next to the defective chip.
As for the other references stated above, the methods described therein have similar problems; i.e., if an excessive current or voltage is applied or a voltage applied is lower than an operating voltage, a defective chip may not be possibly identified. Besides, the technique of Japanese Patent Application Laid-Open No. 2-90549 has a disadvantage in that a dedicated memory cell is necessary.